The present invention relates to a semiconductor device and an electronic device using a reference potential for logical value determination levels corresponding to interface signals for semiconductor chips. More particularly, the invention relates to a technology appropriately applicable to a semiconductor device mounted with a memory chip and a control chip in accordance with an SiP (System In Package) or POP (Package On Package) technique.
A reference potential may be used to determine logical values corresponding to interface signals for multiple semiconductor chips such as a memory chip and a control chip. A resistance voltage division circuit for power supply voltage can be used outside the semiconductor chips to generate the reference potential and supply it to each of the semiconductor chips. However, a large through-current flows when the resistance voltage division circuit using discrete devices generates the reference potential outside the semiconductor chips. This hinders energy saving for battery-driven mobile terminals. To solve this problem, patent document 1 discloses the configuration that provides a reference potential generation circuit inside the semiconductor chip and allows this chip to supply a reference potential to other chips. Patent document 2 discloses the configuration that provides a memory controller with a logical threshold voltage output circuit as a reference potential generation circuit and supplies a reference potential generated from this circuit to an on-chip terminated DRAM chip. Patent document 3 describes the reference potential generation circuit independently provided for each of a memory chip and a control chip mounted on a semiconductor device. Patent document 4 describes the memory module including a decoupling capacitor near a reference potential pin of a memory chip.
Patent document 1: Japanese Unexamined Patent Publication No. 2008-293206
Patent document 2: Japanese Unexamined Patent Publication No. 2004-62725
Patent document 3: Japanese Unexamined Patent Publication No. 2008-4579
Patent document 4: Japanese Unexamined Patent Publication No. 2006-173409
The inventors examined noise suppression when a reference potential generated from one semiconductor integrated circuit is supplied to the other semiconductor integrated circuits. Patent document 1 describes no considerations about the noise suppression on signal paths for transmitting the reference potential. Normally, the bypass capacitor as exemplified in patent documents 2 through 4 suppresses noises on signal paths. A connecting noise or a power supply noise is superimposed on a signal path. The inventors found that it is not always optimal to suppress noises at any position of the signal path. For example, let us suppose that a power supply noise varies the power supply voltage. A signal subject to the power supply variation is preferably processed if the reference potential as a determination level is also subject to a level variation. Let us consider that one semiconductor integrated circuit outputs the reference potential from an output buffer to a signal path and transmits it to another semiconductor integrated circuit and that the former semiconductor integrated circuit delays the reference potential on the signal path and supplies it as a feedback input to an input terminal. The same power supply noise is not expected to be superimposed in an input buffer on the feedback input path if a bypass capacitor is provided near the output side of the signal path to suppress power supply noise components in the reference potential. The inventors found that the feedback-input reference potential might not be used as the signal level determination reference when the reference potential is output. For example, such a case applies when a reference potential is supplied as feedback input to a semiconductor integrated circuit having the self-test function that verifies the reference potential once output outside the chip.
It is an object of the invention to provide a semiconductor device and an electronic device capable of easily allowing a bypass capacitor to always improve noise suppression on a signal path in order to transmit a reference potential between chips in different power supply noise states.
These and other objects and novel features of the invention may be readily ascertained by referring to the following description and appended drawings.
The following summarizes representative aspects of the invention disclosed in this application.
There is provided a specified signal path that connects a control chip and a memory chip mounted on a mounting substrate and transmits a reference potential generated from the control chip. A bypass capacitor is connected to the specified signal path only at a connecting part where a distance from a reference potential pad of the memory chip to the connecting part along the specified signal path is shorter than a distance from a reference potential pad of the control chip to the connecting part along the specified signal path.
According to this restriction, the bypass capacitor more greatly suppresses noises on the reference potential toward the memory chip prone to different power supply noise states than toward the control chip. The reference potential as a criterion becomes more stable on the memory chip. The control chip may receive a feedback of the reference potential and use the feedback for the determination. The feedback reference potential can retain traces of the power supply noise and provide a criterion for signals influenced by the power supply noise.
The following summarizes an effect provided by the representative aspects of the invention disclosed in this application.
The positional restriction on the bypass capacitor makes it possible to allow the bypass capacitor to easily improve noise suppression on a signal path in order to transmit a reference potential between chips in different power supply noise states.